====== 4. Interface ======

===== 4.1 General Considerations =====

  * The host connector and IOL connectors are 2,54mm pitch pin header with a pin length of 6mm.
  * The clearance under the board shall be min. H=3,5mm.

{{ .:pasted:20260915-182825.png?280 }}

===== 4.2 Power Supply =====

  * The 24V power supply voltage shall be 24V +/- 20%.
  * The host connector shall be able to provide 2A on the 24V supply.
  * The voltage is filtered to provide EMC compatibility on the IOL ports when integrated.

<WRAP Important>

Please note that the 24V voltage supply is not reverse polarity protected.
</WRAP>


===== 4.3 Host Connector X1 =====

  * The Vdd provides a reference level for the logic communication (SPI, IRQ) and supply for the µC on the module (IOL Core4 µC only)
  * The Vdd voltage is 3,3V +/- 10%. The maximum current on this line is:
    * IOL Core4 (PT-1204) <20mA.
    * IOL Core4 µC (PT-1205) <75mA.
  * The logic communication lines (SPI, IRQ) do not include ESD protection in order to preserve signal integrity. This needs to be considered on the host if the lines are ESD-exposed.

**Pin assignment:**

^ Pin  ^ Signal  ^
| 1,2  | 24V IN  |
| 3,4  | GND  |
| 5  | Vdd, logic reference (3.2V) |
| 6  | SPI CLK (logic level) |
| 7  | SPI MOSI (logic level) |
| 8  | SPI MISO (logic level) |
| 9  | IRQ1 (logic level) to MAX1 – has an internal pull-up |
| 10  | CS1 (logic level) to MAX1 |
| 11  | IRQ2 (logic level) to MAX2 – has an internal pull-up |
| 12  | CS2 (logic level) to MAX2 |

**Host connector X1 TOP view:**

{{.:pasted:20260915-183325.png?120}}

<WRAP Info>

All logic signals (SPI, interrupts) host interface X1 work on 3V3 logic levels.

</WRAP>

===== 4.4 IOL Connector =====

**Pin assignment:**

^ Pin  ^ Port  ^ Signal ^
| 1  | @lightgreen:  Port 1 (IOL1A)  | @lightgreen: L+  |
| 2  | @orange: Port 2 (IOL1B)  | @orange: L+  |
| 3  | @lightgreen: Port 1 (IOL1A)  | @lightgreen: DIA  |
| 4  | @orange: Port 2 (IOL1B)  | @orange: DIA  |
| 5  | @lightgreen: Port 1 (IOL1A)  | @lightgreen: CQB  |
| 6  | @orange: Port 2 (IOL1B)  | @orange: CQB  |
| 7  | @lavender: Port 3 (IOL2A)  | @lavender: L+  |
| 8  | @lightblue: Port 4 (IOL2B)  | @lightblue:L+  |
| 9  | @lavender: Port 3 (IOL2A)  | @lavender: DIA  |
| 10  | @lightblue: Port 4 (IOL2B)  | @lightblue:DIA  |
| 11  | @lavender: Port 3 (IOL2A)  | @lavender: CQB  |
| 12  | @lightblue: Port 4 (IOL2B)  | @lightblue: CQB  |
| 13,14 | Common  | GND  |

**IOL connector X2 TOP view:**

{{.:pasted:20260915-184307.png}}

<WRAP Important>

Each SDCI Port is designed to supply max. 500mA on the L+ line and 150mA on the CQ line. The current supply is limited by software (for L+ in connection with a series resistor). If a custom master application is used, the limits must be set in the driver configuration.

</WRAP>